1. Full-time bachelor degree or above, major in electronics or microelectronics;
2. More than two years of high-speed dedicated FPGA or CPLD design experience, experience in Altera PLD development is preferred;
3. Familiar with FPGA design and development process, familiar with VHDL / Verilog language, familiar with Xilinx / altera device application, familiar with related comprehensive simulation software;
4. Familiar with common bus protocols, such as I2C \ PCIe \ SPI \ MDIO, etc., have FPGA debugging experience and hardware circuit debugging experience, and be familiar with the use of common instruments.
5. Good English reading ability, strong sense of responsibility, proactive work, and strong sense of teamwork.